module top;
integer ia,ib,is;
reg a,b,s;
wire out;
mux2_structural mux2(out,a,b,s);
initial
begin
for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib + 1)
begin
b = ib;
for (is=0; is<=1; is = is + 1)
begin
s = is;
#1 $display("a=%d b=%d s=%d out=%d",a,b,s,out);
end
end
end
end
endmodule
//二位元多工器
module mux2_structural(OUT, A, B, SEL);
output [1:0]OUT;
input [1:0]A,B;
input SEL;
mux1 hi (OUT[1], A[1], B[1], SEL);
mux1 lo (OUT[0], A[0], B[0], SEL);
endmodule
//一位元多工器
module mux1(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I1 (sel_n, SEL);
and I2 (sel_a, A, SEL);
and I3 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
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