text

module top;
  integer ia,ib,ic,id;
  reg  a,b,c,d;
  wire out;

  mux_structural mux1(out,a,b,c,d);

  initial
    begin
      for (ia=0; ia<=1; ia = ia+1)
        begin
          a = ia;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
              for (ic=0; ic<=1; ic = ic + 1)
               begin
                 c = ic;
for (id=0; id<=1; id = id+1)
        begin
          d = id;
                 #1 $display("a=%d b=%d c=%d d=%d   out=%d",a,b,c,d,out);
               end
            end
        end
    end
end
endmodule

module mux_structural(out, a, b, c, d);
 output out;
 input a,b,c,d;

not n1 (x1, a);
not n2 (x2, b);
not n3 (x3, c);
not n4 (x4, d);

and a1 (f1,x1,x3,d)
and a2 (f2,x1,c,d )
and a3 (f3,b,c,d )
and a4 (f4,a,c,d )
and a5 (f5,x2,c,d )
and a6 (f6,x1,b,x3 )
and a7 (f7,a,x2,x4 )

or o1 (out, f1, f2, f3, f4, f5, f6, f7);

endmodule

加法器

課本 P29

structural
output carry_out, sum;
input a, b, carry_in;
and I1 (a1, b, a);
xor I2 (x1, b, a);
and I3 (a2, x1, carry_in);
xor I4 (sum, x1, carry_in);
or I5 (carry_out, a1, a2);

布林
input
I1 = a&b
I2 = a^b
I3 = (a^b)&carry_in
output
sum = I4 = (a^b)^carry_in
carry_out = I5 = (a&b)+[(a^b)&carry_in]

判斷正確與否

波形圖

2位元多工器 有問題

module top;

integer ia,ib,is;
reg  a,b,s;
wire out;

mux2_structural mux2(out,a,b,s);

  initial
    begin
      for (ia=0; ia<=1; ia = ia+1)
        begin
          a = ia;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
              for (is=0; is<=1; is = is + 1)
               begin
                 s = is;
                 #1 $display("a=%d b=%d s=%d out=%d",a,b,s,out);
               end
            end
        end
    end

endmodule

//二位元多工器
module mux2_structural(OUT, A, B, SEL);
output [1:0]OUT;
input [1:0]A,B;
input SEL;

mux1 hi (OUT[1], A[1], B[1], SEL);
mux1 lo (OUT[0], A[0], B[0], SEL);
endmodule

//一位元多工器
module mux1(OUT, A, B, SEL);
output OUT;
input A,B,SEL;

not I1 (sel_n, SEL);
and I2 (sel_a, A, SEL);
and I3 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

一位元多工器 Part2

not n1(sel_n, SEL);

and a1(sel_a, A, sel_n);
and a2(sel_b, SEL, B);

or o1(OUT, sel_a, sel_b);

一位元多工器 Part1

not n1(sel_n, SEL);

and a1(sel_a, A, SEL);
and a2(sel_b, sel_n, B);

or o1(OUT, sel_a, sel_b);

二個AND閘

原本的AND閘程式，參數從原本的 A, B, OUT 改成 A, B, C, X, F。
Intput : A, B, C
Output : X, F
設定 a1以及 a2 二個AND閘

程式中：
a1     (OUT         , A, B )
          輸出           輸入

A, B 輸入 a1 輸出 X
X, C 輸入 a2 輸出 F

第一次使用SynaptiCAD AND閘

Hardware Description Language

第一天上課

第一次使用blog

老師網站

http://dyu9502.blogspot.tw/