integer ia,ib,ic,id;
reg a,b,c,d;
wire out;
mux_structural mux1(out,a,b,c,d);
initial
begin
for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib + 1)
begin
b = ib;
for (ic=0; ic<=1; ic = ic + 1)
begin
c = ic;
for (id=0; id<=1; id = id+1)
begin
d = id;
#1 $display("a=%d b=%d c=%d d=%d out=%d",a,b,c,d,out);
end
end
end
end
end
endmodule
module mux_structural(out, a, b, c, d);
output out;
input a,b,c,d;
not n1 (x1, a);
not n2 (x2, b);
not n3 (x3, c);
not n4 (x4, d);
and a1 (f1,x1,x3,d)
and a2 (f2,x1,c,d )
and a3 (f3,b,c,d )
and a4 (f4,a,c,d )
and a5 (f5,x2,c,d )
and a6 (f6,x1,b,x3 )
and a7 (f7,a,x2,x4 )
or o1 (out, f1, f2, f3, f4, f5, f6, f7);
endmodule
